View MC34271_137033.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC34271 Liquid Crystal Display and Backlight Integrated Controller
The MC34271 is a low power dual switching voltage regulator, specifically designed for handheld and laptop applications, to provide several regulated output voltages using a minimum of external parts. Two uncommitted switching regulators feature a very low standby bias current of 5.0 A, and an operating current of 7.0 mA capable of supplying output currents in excess of 200 mA. Both devices have three additional features. The first is an ELD Output that can be used to drive a backlight or a liquid crystal display. The ELD output frequency is the clock divided by 256. The second feature allows four additional output bias voltages, in specific proportions to VB, one of the switching regulated output voltages. It allows use of mixed logic circuitry and provides a voltage bias for N-Channel load control MOSFETst. The third feature is an Enable input that allows a logic level signal to turn-"off" or turn-"on" both switching regulators. Due to the low bias current specifications, this device is ideally suited for battery powered computer, consumer, and industrial equipment where an extension of useful battery life is desirable.
MC34271 Features: http://onsemi.com
32 1
QFP-32 FB SUFFIX CASE 873
PIN CONNECTIONS AND MARKING DIAGRAM
32 SW1 31 Sync 30 RT 29 Gnd 28 VA 27 Vref 26 EN1 V1 15 25 EN2 DS2 24 Ref2 23 AWLYYWW FB2 22 Comp2 21 SS2 20 S2 19 D2 18 Mode VDD ELD V4 V3 V2 V0 16 VB 17 MC34271
1 DS1 2 Ref1 3 FB1 4 Comp1 5 SS1 6 S1 7 D1 8 Drv1
* Low Standby Bias Current of 5.0 A * Uncommitted Switching Regulators Allow Both Positive and * * * * *
Negative Supply Voltages Logic Enable Allows Microprocessor Control of All Outputs Synchronizable to External Clock Mode Commandable for ELD and LCD Interface Frequency Synchronizable Auxiliary Output Bias Voltages Enable Load Control via N-Channel FETs
Rating Input Voltage Symbol VDD Value 16 Unit Vdc
9
10
11
12
13
14
(Top View) A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
MAXIMUM RATINGS (TA = 25C, unless otherwise noted.)
AAA A A A AAAAAAAAAAAAAAAAAAAA AAA AAA A A A AAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAA AA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAA AAA AAA A A A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AA
Power Dissipation and Thermal Characteristics Maximum Power Dissipation - Case 873 Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Output #1 and #2 Switch Current PD RJA RJC VSL VLF TJ 1.43 100 60 500 60 20 W C/W C/W mA ISL & ISB Output #1 and #2 "Off"-State Voltage Feedback Enable MOSFETs "Off"-State Voltage Vdc Vdc C C C Operating Junction Temperature Operating Ambient Temperature Storage Temperature Range 125 TA 0 to +70 Tstg - 55 to +150
(c) Semiconductor Components Industries, LLC, 2000
ORDERING INFORMATION
Device MC34271FB Package QFP-32 Shipping 250 Units / Tray
1
April, 2000 - Rev. 0
Publication Order Number: MC34271/D
MC34271
Representative Block Diagram
Vin SW1 32 EL Panel EL Control On/Off EN1 26 VDD D1 7 S1 6 ELD 9 8 Sync 31 RT 30 VRef 27 Ref1 FB1 Comp1 4 P Control EN2 25 V0 From DAC VB Ref2 FB2 23 22 Comp2 21 V2 14 VA = 5.0 V 28 Gnd 29 12 BIAS Output Buffers BIAS 13 V4 V3 V3 V2 15 16 V1 V0 17 VB VB 2 3 Vref 1.25 V /2 OSC ELD EN VDD VDD 11 Mode 10 D2 Circuit #2 PWM 18 19 S2 Vin
Circuit #1 PWM
Drv1
V1
V4
This device contains 350 active transistors.
http://onsemi.com
2
MC34271
ELECTRICAL CHARACTERISTICS (VDD = 6.0 V, for typical values TA = Low to High [Note 1], for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted.)
Characteristic REFERENCE SECTION Reference Voltage (TJ = 25C) Line Regulation (VDD = 5.0 V to 12.5 V) Load Regulation (IO = 0 to 120 A) Total Variation (Line, Load and Temperature) ERROR AMPLIFIERS Input Offset Voltage (VCM = 1.25 V) Input Bias Current (VCM = 1.25 V) Open Loop Voltage Gain (VCM = 1.25 V, VCOMP = 2.0 V) Output Voltage Swing High State (IOH = -100 A) Low State (IOL = 100 A) BIAS VOLTAGE Voltage (VDD = 5.0 V to 12.5 V, IO = 0) OSCILLATOR AND PWM SECTIONS Total Frequency Variation Over Line and Temperature VDD = 5.0 V to 10 V, TA = 0 to 70C, RT = 169 k Duty Cycle at Each Output Maximum Minimum Sync Input Input Resistance (Vsync = 3.5 V) Minimum Sync Pulse Width OUTPUT MOSFETs Output Voltage - "On"-State (Isink = 200 mA) Output Current - "Off"-State (VOH = 40 V) Rise and Fall Times EL DISCHARGE OUTPUT (ELD) AND DRV1 Output Voltage - "On"-State (Isink = 100 A) Output Voltage - "On"-State (Isink = 50 mA) Output Voltage - "Off"-State (Isource = -100 A) Output Voltage - "Off"-State (Isource = - 50 mA) FEEDBACK ENABLE SWITCHES (DS1, DS2) Output Voltage - "Low"-State (Isink = 1.0 mA) Output Current - "Off"-State (VOH = 12.5 V) SWITCHED VDD OUTPUT (SW1) Output Voltage Switch "On" (EN1 = 1, Isource = 100 A) Switch "Off" (EN1 = 0, Isink = 100 A) AUXILIARY VOLTAGE OUTPUTS V0 Enable Switch "On"-Resistance: VB to V0 "Off"-State Leakage Current (VB = 10 V) V0 Voltage (VB = 30 V, Isource = 0 mA) V0 Resistance (Isource = 4.0 mA) Rds Ilkg V0 R0 0 0 29.5 20 2.0 0.1 29.9 40 10 2.0 30 60 A V V VswOH VswOL 5.5 0 5.9 0.1 6.0 0.2 VfeOL IfeOH - - 10 0.6 100 1.0 mV A VOL VOL VOH VOH - - VDD-0.5 VDD-3.5 30 2.0 5.9 3.3 100 2.5 - - mV V V V VOL IOH tr, tf - - - 150 0.1 50 250 1.0 - mV A ns fOSC 90 DCmax DCmin Rsync Tp 92 - 25 - 115 95 - 50 1.0 140 % - 0 100 - k s kHz VA 4.6 5.0 5.4 V VIO IIB AVOL VeOH VeOL - - 80 VA-1.5 0 1.0 120 100 4.0 - 10 600 - 5.5 1.0 mV nA dB V Vref Regline Regload Vref 1.225 - - 1.215 1.250 2.0 2.0 - 1.275 10 10 1.285 V mV mV V Symbol Min Typ Max Unit
NOTE: 1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
http://onsemi.com
3
MC34271
ELECTRICAL CHARACTERISTICS (continued) (VDD = 6.0 V, for typical values TA = Low to High [Note 1], for min/max values TA is
the operating ambient temperature range that applies, unless otherwise noted.) Characteristic AUXILIARY VOLTAGE OUTPUTS V1, V2, V3, V4 Outputs 1-V1/V0 Ratio 1-V2/V0 Ratio V3/V0 Ratio V4/V0 Ratio Output Resistance (Isource = 4.0 mA) Output Short Circuit Current LOGIC INPUTS (EN1, EN2, MODE) Input Low State Input High State Input Impedance SOFT START CONTROL (SS1,SS2) Charge Current (Capacitor Voltage = 1.0 V to 4.0 V) Discharge Current (Capacitor Voltage = 1.0 V) TOTAL SUPPLY CURRENT VDD Current Standby Mode (EN1 = EN2 = 0) VDD Current Backlight "On" (EN1 = 1; EN2 = 0) VDD Current LCD "On" (No Inductor) (EN1 = 0; EN2 = 1) VB Current (V0 = 35 V) VDD = 6.0 V VDD = 16 V ICC ICC ICC IO - - - - - 2.0 3.0 0.7 0.9 1.2 5.0 15 3.0 2.0 3.0 A mA mA mA Ichg Idschg 0.5 250 1.0 650 2.5 - A A VIL VIH Rin 0 2.0 25 - - 50 0.8 6.0 100 V V k 0.0500 0.1010 0.1010 0.0500 20 5.0 0.0520 0.1035 0.1035 0.0520 40 10 0.0535 0.1065 0.1065 0.0535 60 20 Symbol Min Typ Max Unit
Ro Iss
mA
NOTE: 1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
1.0 DC, SWITCH OUTPUT DUTY CYCLE 0.8 0.6 0.4 0.2 0 1.5 VDD = 6.0 V TA = 25C AVOL, OPEN LOOP VOLTAGE GAIN (dB)
100 80 Gain 60 40 20 0 Phase
0 VDD = 6.0 V VComp = 2.5 V 30 RL = Open TA = 25C 60 90 120 150 180 1000 k
2.0
2.5
3.0
3.5
4.0
4.5
- 20 10
100
1.0 k
10 k
100 k
VComp, COMPENSATION VOLTAGE (V)
f, FREQUENCY (Hz)
Figure 1. Switch Output Duty Cycle versus Compensation Voltage
Figure 2. Error Amp Open Loop Gain and Phase versus Frequency
http://onsemi.com
4
MC34271
0 Vref OUTPUT VOLTAGE DROP (mV) QUIESCENT CURRENT (mA) - 5.0 -10 VA -15 - 20 - 25 - 30 0 VDD = 6.0 V TA = 25C 1.0 2.0 3.0 4.0 5.0 2.0 1.5 1.0 0.5 0 2.0 Standby Current EN1 and EN2 = 0 RT = 169 k No Loading TA = 25C 10 12 14 16 EN1 and EN2 = 1 1.8 1.4 1.0 0.6 0.2 18 2.5 2.2
EN1 = 1 and EN2 = 0
4.0
6.0
8.0
I, CURRENT DRAW (mA)
VDD, SUPPLY VOLTAGE (V)
Figure 3. Reference Voltage Change versus Reference Current
Vsat, SWITCH OUTPUT SOURCE SATURATION (V)
Figure 4. Quiescent Current versus Supply Voltage
0.16
0 VDD -1.0 Sink Saturation VDD = 6.0 V TA = 25C
2.0
FET DRAIN VOLTAGE (V)
0.12
1.5
0.08
- 2.0 Source Saturation
1.0
0.04 VDD = 6.0 V TA = 25C 0 0 50 100 ID, DRAIN CURRENT (mA) 150 200
- 3.0
0.5
- 4.0 0
15
30
45
0 60
ISource, SWITCH OUTPUT CURRENT (mA)
Figure 5. FET Drain Voltage versus Sink Current
Figure 6. ELD and DRV1 Switch Output Source and Sink Saturation versus Current
OSCILLATOR FREQUENCY CHANGE (kHz)
0.30 0.25 VOLTAGE VARIATION (V) 0.20 0.15 0.10 0.05 0 Vref VDD = 6.0 V VA
8.0 6.0 4.0 2.0 0 - 2.0 - 4.0 - 6.0 - 8.0 0 10 20 30 40 50
VDD = 6.0 V RT = 169 k
- 0.05 - 0.10 0 10 20 30 40 50 60 70
60
70
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 7. Vref and VA Variation versus Temperature
Figure 8. Oscillator Frequency Variation versus Temperature
http://onsemi.com
5
SWITC O T
T SIN SAT RATION ( )
MC34271
1000 REFERENCE VOLTAGE (V) 5.0 4.0 3.0 2.0 1.0 0 Vref RT = 169 k TA = 25C VA
FREQUENCY (kHz)
VDD = 6.0 V TA = 25C 100
10
0
100 TIMING RESISTANCE (k, s)
1000
0
1.0
2.0
3.0 VDD LEVEL (V)
4.0
5.0
6.0
Figure 9. Frequency versus Timing
Figure 10. VA, Vref versus VDD
OPERATING DESCRIPTION The MC34271 is a monolithic, fixed frequency power switching regulator specifically designed for dc to dc converter and battery powered applications. This device operates as a fixed frequency, voltage mode regulator containing all the active functions required to directly implement step-up, step-down and voltage inverting converters with a minimum number of external components. Potential markets include battery powered, handheld, automotive, computer, industrial and cost sensitive consumer products. A description of each section is given below with the representative block diagram shown in Figure 11.
Oscillator
reference and oscillator, can be activated by either EN1 or EN2. Circuit #1 has an ELD output which may be used to drive an LCD or backlight. Its output frequency is the oscillator frequency divided by 1024.
Error Amplifiers and Reference
The oscillator frequency is programmed by resistor RT. The charge to discharge ratio is controlled to yield a 95% maximum duty cycle at the switch outputs. During the fall time of the internal sawtooth waveform, the oscillator generates an internal blanking pulse that holds the inverting input of the AND gates high, disabling the output switching MOSFETs. The internal sawtooth waveform has a nominal peak voltage of 3.3 V and a valley voltage of 1.7 V.
Pulse Width Modulators
Each error amplifier is provided with access to both inverting and noninverting inputs, and the output. The Error Amplifiers' Common Mode Input Range is 0 to 2.5 V. The amplifiers have a minimum dc voltage gain of 60 dB. The 1.25 V reference has an accuracy of 4.0% at room temperature. External loop compensation is required for converter stability. A simple low-pass filter is formed by connecting a resistive divider from the output to the error amplifier inverting input, and a series resistor-capacitor from the error amplifier output also to the to the inverting input. The step down converter is easiest to compensate for stability. The step-up and voltage inverting configurations, when operated as continuous conduction boost or flyback converters, are more difficult to compensate, and may require a lower loop design bandwidth.
MOSFET Switch Outputs
Both pulse width modulators consist of a comparator with the oscillator ramp voltage applied to the noninverting input, while the error amplifier output is applied to the inverting input. A third input to the comparator has a 0.5 mA typical current source that can be used to implement soft start. Output switch conduction is initiated when the ramp waveform is discharged to the valley voltage. As the ramp voltage increases to a voltage that exceeds the error amplifier output, the latch resets, terminating output MOSFET conduction for the duration of the oscillator ramp. This PWM/latch combination prevents multiple output pulses during a given oscillator cycle. Each PWM circuit is enabled by a logic input. When disabled, the entire block is turned off, drawing only leakage current from the power source. Shared circuits, like the
The output MOSFETs are designed to switch a maximum of 60 V, with a peak drain current capability of 500 mA. In circuit #1 an additional DRV1 output is provided for interfacing with an external MOSFET.The gates of the MOSFETs are held low when the circuit is disabled.
Auxiliary Output Voltages
Output voltages V0 through V4 are provided for use as references or bias voltages. V0 is the circuit #2 output voltage, when an internal FET switch is activated. The other auxiliary output voltages are proportional to VB. The amplifiers for V1 and V2 are powered from V0, while the amplifiers for V3 and V4 are powered from VDD.
http://onsemi.com
6
MC34271
Figure 11. Representative Block Diagram Electroluminescent Backlight Configuration
SW1 32 DS1 EL Panel 1 EN1 26 8 Drv1 /2 31 Sync 169 k 30 RT 27 2 3 Brightness VB FB1 Vref 1.25 V Ref1
Circuit #1 Bias Supply En S Q R VDD
D1 7 S1 6 ELD 9 VDD 11 Mode 10 D2 VDD "On/Off"
4 Comp1 SS1 5
VDD2 Circuit #2 Bias Supply
DAC
Ref2 23 22 FB2 Comp2 21 SS2 20 DS2 24
25 EN2
VA 28 Gnd 29
BIAS
http://onsemi.com
7
II II
I I I I
/N
OSC
S Q R En VDD
18 S2 19
VB 17 V0 16 V1 15 V2 14 VDD2 V3 13 VDD2 V4 12 V4 V3 V2 V1 V0
VB 6.0 V to 30 V
LCD Display
MC34271
Figure 12. Auxiliary Supply Configuration
12 V SW1 32 DS1 1 EN1 26 S Q R Circuit #1 Bias Supply En D1 7 S1 6 ELD 9 VDD OSC Mode 10 Vref 1.25 V Ref1 S R En Q D2 18 S2 19 11 VDD 5.0 V to 16 V
- 27 V
8 Drv1
31 Sync 169 k 30 RT 27 2 3 12 V
VB LCD Contrast DAC
4 Comp1 SS1 5
VDD2 Circuit #2 Bias Supply
Ref2 23 22 FB2 Comp2 21 SS2 20 DS2 24
25 EN2
VA 28 Gnd 29
BIAS
http://onsemi.com
8
II I I
FB1
I II I I
VDD /2
/N
VDD
VB 17 V0 16 V1 15 V2 14 VDD2 V3 13 VDD2 V4 12 V4 V3 LCD Display V2 V1 V0
VB 6.0 V to 30 V
MC34271
Figure 13. EL PANEL Drive Circuit
Vin 6.0 V + MC34271 2.2 M SW1 32 Circuit #1 Bias Supply En S Q R 26 8 Drv1 31 Sync 160 k 9.1 k 30 RT D2 S R Q 18 S2 19 2.2 k VDD /2 D1 7 S1 6 ELD 9 VDD OSC Mode 10 11 10 MTP3055EL 400 Hz 0.1 F 4T #36 6
10 F MR856 8 3 4T #36 5 4 120T 1 #36 7 MPSA44 120T #36 2 MR856 1.0 k 0.22 F 200 V 15 k EL PANEL
8.25 k
Vref Vref 1.25 V 0.1 27 F 2 Ref1
22 k 1.0 k 10 k
VDD2 Circuit #2 Bias Supply
MMBT2907 1
DS1 Ref2 23 22 FB2 Comp2 21 SS2 20 DS2 24 V1 15 25 EN2 V2 14 VA 28 Gnd 29 VDD2 V3 13 VDD2 V4 12 V4 V3 LCD Display V2 V1 VB 17 V0 16 V0
1.0 k VB
DAC
8.2 k
BIAS
NOTES::1. Transformer information TDK Core # PC40EEM12.7/13.7-Z Bobbin # BEPC-10-118G 2 mil gap. LP = 1.6 hy. 2. EL PANEL: DURELTM 3/SL ORANGE
http://onsemi.com
9
II I I
4.3 M 15 pF
3 FB1 4 Comp1 SS1 0.1 F 5
I II I I
EN1
/N
VDD
VB
MC34271
PACKAGE DIMENSIONS
QFP-32 FB SUFFIX CASE 873-01 ISSUE A L
24 25
17 16 S
D
S
0.20 (0.008) M C A-B 0.05 (0.002) A-B
-A- L
-B- B
0.20 (0.008)
M
V
H A-B
S
D
S
B P
DETAIL A
32 1 8 9
B
-D- A 0.20 (0.008) M C A-B 0.05 (0.002) A-B S 0.20 (0.008)
M S
-A-,-B-,-D- D
S
DETAIL A
H A-B
S
D
S
BASE METAL
F
M
DETAIL C J N D 0.20 (0.008)
M
CE -C-
SEATING PLANE
-H- H G M
DATUM PLANE
0.01 (0.004)
C A-B
S
D
S
SECTION B-B
VIEW ROTATED 90 CLOCKWISE MILLIMETERS MIN MAX 6.95 7.10 6.95 7.10 1.40 1.60 0.273 0.373 1.30 1.50 0.273 - 0.80 BSC - 0.20 0.119 0.197 0.33 0.57 5.6 REF 6 8 0.119 0.135 0.40 BSC 5 10 0.15 0.25 8.85 9.15 0.15 0.25 5 11 8.85 9.15 1.0 REF INCHES MIN MAX 0.274 0.280 0.274 0.280 0.055 0.063 0.010 0.015 0.051 0.059 - 0.010 0.031 BSC 0.008 - 0.005 0.008 0.013 0.022 0.220 REF 8 6 0.005 0.005 0.016 BSC 10 5 0.006 0.010 0.348 0.360 0.006 0.010 11 5 0.348 0.360 0.039 REF
U
T -H- DATUM PLANE K X DETAIL C R
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V X
http://onsemi.com
10
MC34271
Notes
http://onsemi.com
11
MC34271
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local Sales Representative.
http://onsemi.com
12
MC34271/D

▲Up To Search▲

Price & Availability of MC34271

	To Download MC34271 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .